1. Field of the Invention
The present invention is related generally to local power supplies for integrated circuits with a high clock frequency, and in particular to circuits for use in limiting inductance-induced ripple voltage in integrated circuits with high dynamic power consumption.
2. Description of Related Art
Over the past few years clock speeds of central processing units (CPUs) have increased from a few MHz to 500 MHz or more. This increase in clock speed requires that components within the CPU, i.e., the CPU core, as well as components that communicate with the CPU operate at ever increasing clock speeds.
The increase in CPU clock speeds has been accompanied by an increase in the number of transistors on the CPU die, i.e., in the integration on the chip. The greater integration results in a larger die size, which in turn means that some circuits on the die are separated by greater distances, and in addition, more pins are required to take information to and from the die. Both of these effects complicate electromagnetic interference (EMI) shielding at the higher clock speeds.
FIG. 1 is a first order lumped model of a typical CPU configuration as seen by the power supply pins. A first inductor 145 represents the inductance of the board plane and via layer, and is connected to power supply line 110. Connected in series with inductor 145 is a second inductor 140 that represents the inductance of the socket and packaging of the CPU. Connected in series with inductors 140 and 145 is a series combination of a third inductor 137 and a resistor 135. The series combination of third inductor 137 and resistor 135 represents the inductance and resistance, respectively of either a ball grid array, or a lead frame with bond wires, and the power grid of CPU 100. The CPU die has an intrinsic RC characteristic that is represented by a series combination of resistor 151 and capacitor 152 connected to resistor 135 by local power supply line 110A and to ground line 111 by local power supply line 111A.
Typically, at the start of each clock cycle, many elements in CPU 100 change state, which in turn causes a momentary increase in current draw, i.e., the current draw changes as a function of time. The voltage generated by inductors 145, 140 and 137 is directly proportional to the changes in current with respect to time. Specifically, as the time derivative of the current increases, inductors 145, 140, 137 create a positive voltage drop which in turn reduces the voltage across local power supply lines 110A and 111A. Consequently, sufficient power cannot be provided instantaneously to the elements in the CPU core changing state, and so the voltage difference between local power supply lines 110A and 111A decreases, i.e., collapses.
However, once the various elements have switched state, the change in current draw with respect to time diminishes and the voltage difference recovers. In addition, inductors 145, 140, and 137 supplement the voltage across local power supply lines 110A and 111A because the time derivative of the current is negative.
These swings in voltages caused by the inherent inductances, including parasitic inductances, in response to changes in the current draw over time, are called inductance-induced ripple voltages or sometimes simply bounce. The inductance-induced ripple voltages have many undesirable features. For example, if the voltage collapse is too great, operation of CPU 100 can become unreliable. Also, the inductance-induced ripple voltages radiate from at least the pins of the circuit, and can radiate from power supply lines in CPU 100 that function as antennas. This requires additional shielding or other design changes to assure that CPU 100 complies with all relevant EMI standards. Additionally, if the frequency of the inductance-induced ripple voltage approaches the resonance frequency of the package, the voltage collapse and EMI noise is effectively amplified which in turn further exacerbates the problems associated with the parasitic inductances.
Various techniques have been used to minimize the effects of the inductance-induced ripple voltages in attempting to provide a stable power supply voltage across a CPU core. Specifically, power supply decoupling was normally achieved by placing banks of capacitors on the die between the local power supply lines carrying power supply and ground potentials so as to minimize the effects of parasitic inductances and resistances. However, each bank of capacitors has a limited band in the frequency spectrum where the bank is effective in smoothing out the inductance-induced ripple voltage, and has a limited capacity to decouple.
Moreover, as both the power consumption and the clocking speeds increased, the switching current at local power nodes within the integrated circuit required a relatively large capacitance to offset the power losses associated with the parasitic board and package inductances near the resonance frequency of the package. This, in turn, meant that a larger number of high frequency capacitors were required.
However, as the high frequency circuits become more highly integrated, the real estate on the die available for capacitors diminished as the requirement for the number of capacitors increased due to the increased power consumption. This limitation forced consideration of alternative physical and manufacturing configurations to provide the required amount of passive capacitance.
A first approach was to connect passive capacitance 160 on the board between the CPU socket power supply connectors and ground, i.e., between the connection of inductors 145 and 140 and ground as illustrated in FIG. 2A. It should be understood that passive capacitance 160 includes parasitic inductance and resistance that are connected in series with passive capacitance 160. However, this approach was not completely successful because this configuration did not effectively offset the effects of inductors 140 and 137.
Consequently, some manufacturers use discrete capacitors that are placed on top or below the package. In this configuration, passive capacitance 165 is connected between inductors 140 and 137 and ground as illustrated in FIG. 2B. While this configuration is better than the configuration of FIG. 2A, passive capacitance 165 does not directly affect the voltage across local power supply lines 110A and 111A.
Hence, other manufacturers include a separate chip of low inductance capacitors in the package containing the high frequency die and attempt to connect capacitance 170 on the separate chip between local power supply line 110A and 111A as shown in FIG. 2C.
While the current manufacturing techniques and physical configurations may be adequate for current microprocessor clock speeds and power consumption, as the power consumption and clock speeds continue to increase other solutions will be required. Unfortunately, the next generation of high-speed circuits will draw even more power, because typically the power consumption is proportional to the clock speed. With the higher power consumption and the fast clock speeds, the changes in the time derivative of the current will be more extreme which in turn indicates problems associated with inductance-induced ripple voltages will be further exacerbated.
The solution to power supply inductance-induced ripple voltages appears to be limited to the use of passive capacitors. Other techniques for offsetting the effects of parasitic inductance and resistance are not of use considering the feature sizes of the next generation of integrated circuits. Consequently, the dynamic power consumption of future generations of circuits may be limited by the inability to effectively offset the effects of parasitic inductances and resistances on power supply voltages.
In accordance with the principles of this invention, an active digital voltage regulator circuit overcomes the problems with stabilizing on-board power supply voltages for a high-frequency integrated circuit where parasitic inductance and resistance affect local power supply voltages. The active digital voltage regulator circuit is a two terminal device that is connected in shunt to the first and second power supply input lines, that in turn are connected to a circuit block that draws power from first and second power supply input lines.
The active digital voltage regulator circuit stores energy during times when the local power supply voltage is greater than a predefined voltage, e.g., during times when the parasitic inductances supplement the local power supply voltage. The active digital voltage regulator circuit uses the stored energy to supplement the local power supply voltage during times when the local power supply voltage starts to collapse, e.g., during periods when inductive losses are preventing the power supply from maintaining the local power supply voltage. Consequently, the digital active voltage regulator circuit smoothes the local power supply voltage by greatly ameliorating the ripple voltages associated with parasitic inductances and resistances.
The reduction in local power supply voltage variations caused by parasitic inductances has many advantages. First, the problems associated with local power supply voltage collapse are eliminated, and so the clock speeds and the associated dynamic power consumption can be increased over those attainable with only passive capacitance. Second, since the local power supply voltage is more stable at the increased clock speeds, any EMI problems associated with parasitic inductance-induced ripple voltages are minimized which in turn reduces the requirements for EMI suppression. Further, the packaging problems introduced by the requirements for ever increasing numbers of passive capacitors is eliminated. In addition, with the digital active voltage regulator of this invention, die area constraints no longer make on-chip power supply voltage stabilization impossible.
Hence, according to the principles of the invention, in one embodiment, the active digital voltage regulator circuit connects a plurality of capacitive elements in parallel across the first and second power supply input lines to charge the plurality of capacitive elements when the inductance-induced ripple voltages raise a voltage on the first and second power supply lines. Conversely, the digital active voltage regulator circuit connects the plurality of capacitive elements in series across the first and second power supply input lines to discharge the plurality of capacitive elements onto the first and second power supply lines when the inductance-induced ripple voltages lower a voltage on the first and power supply lines.
In one embodiment, the digital active voltage regulator circuit has a first capacitive element with a first lead connected to the first power supply input line and a second lead. A second capacitive element has a first lead connected to the second power supply input line and a second lead.
A first switch element is connected to the second lead of the first capacitive element and to the second power supply input line. In one embodiment, the first switch element is a MOSFET of a first type. The first switch element has an open state, and a closed state.
A second switch element is connected to the second lead of the second capacitive element, and to the first power supply input line. In one embodiment, the second switch element is a MOSFET of a second type. The second switch element also has an open state, and a closed state.
A third switch element is connected to the second lead of the first capacitive element and to the second lead of the second capacitive element. In one embodiment, the third switch element is a CMOS transmission gate. The third switch element has an open state, and a closed state.
A control circuit within the digital active voltage regulator is connected to the three switches, and configures the three switches so that the operations described above are performed by the digital active voltage regulator circuit. The control circuit changes the state of each of the first, second, and third switch elements with a break-before-make characteristic.
The control circuit can be implemented as a reactive control circuit, a predictive control circuit, and a deterministic control circuit. The reactive control circuit generates a reference voltage and then monitors an instantaneous threshold voltage to determine when to change the state of the switches. With the reactive control circuit, changes in the instantaneous threshold voltage relative to the reference voltage determine when the configuration of the capacitors is changed from shunt to series.
The predictive control circuit monitors a reference voltage to determine when to change the state of the switches. With the predictive control circuit, changes in the reference voltage relative to instantaneous threshold voltage determine when the configuration of the capacitors is changed from shunt to series. The deterministic control circuit is similar to the predictive control circuit, except the reference voltage is changed at deterministic time intervals.
In one embodiment, the control circuit is a combination of two self-biasing and offset-nulling power supply monitor circuits. Each self-biasing and offset nulling power supply monitor circuit has only the two power supply input lines and two output lines. One of the output lines is connected to one of switches used to place the capacitors in shunt, and the other output line is connected to the transmission gate that is used to place the capacitors in series.
Each self-biasing and offset-nulling power supply monitor circuit includes a first power supply input line, a second power supply input line, a first power supply monitor output line, a second power supply monitor output line, and a feedback line connected to one of the first and second power supply monitor output lines. Hence, one of the power supply monitor circuits has the feedback line connected to the second power supply monitor output line, and the other of the power supply monitor circuits has the feedback line connected to the first power supply monitor output line.
Each power supply monitor circuit also includes a reference voltage generator connected to first and second power supply input lines. The reference voltage generator has an input line connected to the feedback line, and a reference voltage generator output line. The reference voltage generator generates a reference voltage on the reference voltage output line.
Each power supply monitor circuit further includes a differencing non-overlapped, dual-output amplifier connected to the first and second power supply input lines. This amplifier has an amplifier input line connected to the reference voltage generator output line; a first output terminal coupled to the first (third) power supply monitor output line; and a second output terminal coupled to the second (fourth) power supply monitor output line.
In a quiescent state, a first output signal on the first power supply monitor output line of the amplifier has a first level; and a second output signal on the second power supply monitor output line of the amplifier has a second level. The second signal level is offset from the first signal level. The first and second output signals swing to a first voltage level, but reach the first voltage level at different points in time so that the first and second output signals are offset and non-overlapping for a period of time during the swing.
In one embodiment, the reference voltage generator includes a feedback driver connected to the first and second power supply input lines. The feedback driver has an input terminal connected to the reference voltage generator input line; and a feedback driver output terminal coupled to the reference voltage generator output line.
A capacitive element in the reference voltage generator is connected to one of the first and second power supply input lines, and to the reference voltage generator output line. Thus, in the first power supply monitor circuit, the capacitive element is connected to the first power supply input line, and in the second power supply monitor circuit, the capacitive element is connected to the second power supply line.
In one embodiment, the output impedance of the feedback driver is such that the feedback driver output terminal is connected directly to the reference voltage generator output line. In another embodiment, the output impedance of the feedback driver is lower, and so the feedback driver output terminal is connected to the reference voltage generator output line by a resistive element.
The differencing, non-overlapped, dual-output amplifier includes a predriver stage and an output stage, both of which are connected to the first and second power supply input lines. The predriver stage has an input terminal connected to the amplifier input line. The number of output lines of the predriver stage depends on the implementation of the predriver stage. The output stage has a first output terminal connected to the first(third) power supply monitor output line, and a second output terminal connected to the second(fourth) power supply monitor output line.
In a first embodiment, the predriver stage is a quasi-cascode predriver. The quasi-cascode predriver includes a MOSFET of a first type having a first lead connected to the first power supply input line; a second lead; and a gate connected to the amplifier input line. This embodiment of the predriver stage also includes a MOSFET of a second type having a first lead connected to the second power supply input line; a second lead coupled to the second lead of the MOSFET of the first type; and a gate connected to the amplifier input line. The predriver output line is coupled to the second leads of the MOSFETS of the first and second types.
In a second embodiment, the predriver stage is a first embodiment of an offset dual-output driver. The first embodiment of the offset dual-output driver has a MOSFET of a first type having a first lead connected to the first power supply input line; a second lead; and a gate connected to the amplifier input line. The offset dual-output driver also includes a MOSFET of a second type having a first lead connected to the second power supply input line; a second lead coupled to the second lead of the MOSFET of the first type; and a gate connected to the amplifier input line.
The offset dual-output driver has a first voltage divider connected between the second leads of the MOSFETS of the first and second types, and a second voltage divider connected between the second leads of the MOSFETS of the first and second types. A first predriver output line is connected to a tap of the first voltage divider, and a second predriver output line is connected to a tap of the second voltage divider.
In the first embodiment of the power supply monitor circuit, the output stage is a quasi-class A push-pull driver that is an second embodiment of a offset dual-output driver. Alternatively, the output stage could be the first embodiment of the offset dual-output driver, described above.
The second embodiment of the offset dual-output driver includes a MOSFET of a first type having a first lead connected to the first power supply input line; a second lead; and a gate connected to a predriver output line. The offset dual-output driver also includes a MOSFET of a second type having a first lead connected to the second power supply input line; a second lead coupled to the second lead of the MOSFET of the first type; and a gate connected to the predriver output line. A variable resistance element of the driver has a first lead connected to the second lead of the MOSFET of the first type, and a second lead connected to the second lead of the MOSFET of the second type.
A first output line of offset dual-output driver is connected to the second lead of the MOSFET of the first type. The second output line of this driver is connected to the second lead of the MOSFET of the second type.
When the predriver stage is implemented as the first embodiment of the offset dual-output driver, the output stage includes a high beta inverter having a first input terminal connected to a first predriver stage output line; a second input terminal connected to a second predriver output line; and the first output terminal connected to the first power supply monitor output line. In addition, the output stage includes a low beta inverter having a first input terminal connected to the first predriver stage output line; a second input terminal connected to the second predriver output line; and the second output terminal connected to the second power supply monitor output line.
The self-biasing, offset-nulling power supply monitor of this invention can be used in a wide variety of applications that require comparison of a reference voltage with an instantaneous threshold voltage. Similarly, the differencing, non-overlapped, dual-output amplifier can be utilized in any application in which it is necessary to compare a first input signal on a first input line, with another signal derived from the voltage across the other two terminals of the amplifier. Both the amplifier, and the power supply monitor circuit have the advantages described above.